Error: "(vlog-2110) Illegal reference to net"

I have a simple FIFO code in SystemVerilog. I get several vlog-2110 illegal reference to net error messages. My error messages are followed by my code. Error messages:

vlog -work work -sv -stats=none C:/Users/Single_FIFO.sv Model Technology ModelSim DE vlog 10.4 Compiler 2014.12 Dec 3 2014 -- Compiling module fifo_core_and_cntl
Error: C:/Users/Single_FIFO.sv(24): (vlog-2110) Illegal reference to net "occucy".
Error: C:/Users/Single_FIFO.sv(26): (vlog-2110) Illegal reference to net "empty".
Error: C:/Users/Single_FIFO.sv(28): (vlog-2110) Illegal reference to net "empty".
Error: C:/Users/Single_FIFO.sv(30): (vlog-2110) Illegal reference to net "full".
Error: C:/Users/Single_FIFO.sv(32): (vlog-2110) Illegal reference to net "full". . .

My simple FIFO code: the small offending portion of it, is shown below.

module fifo_core_and_cntl (data_in, data_put, data_get, clk, reset_n, data_out, occucy, empty, full); input [7:0]data_in; input data_put, data_get, clk, reset_n; output [7:0]data_out; output empty, full; output [4:0]occucy; logic [4:0]current_readptr, current_writeptr, next_readptr, next_writeptr; logic [15:0][7:0]data_fifo; // This is data Fifo: 2D packed array of vectors: sixteen 8 bit vectors. always_ff @ (posedge clk, negedge reset_n) // For the Current counter updates. if (!reset_n) begin current_writeptr